1. Field of the Invention
The present invention relates to a jitter generator, and more particularly, to a jitter generator capable of generating a jittered clock signal for being utilized for built-in-self-test (BIST) of a chip.
2. Description of the Prior Art
In digital communication systems, the tolerance ability of a receiver with respect to timing jitter is an important parameter for evaluating the overall system performance, especially in high-speed communication systems. So-called timing jitter means the appearance of a shift of a rising/falling edge of a data signal or a clock signal (that is, phase shift), causing an increased bit error rate (BER) of the receiver. The conventional solutions usually reduce the effect of jitter in the receiver by utilizing a clock and data recovery (CDR) circuit of the receiver.
Therefore, how to test the jitter tolerance of a receiver is always an important topic. A common test method for the conventional architecture comprises utilizing a jitter generator to generate a clock signal having timing jitter, and inputting a series of random test data bits into a D-type flip-flop, where the D-type flip-flop is triggered by the clock signal having timing jitter to operate. In this way, the D-type flip-flop is capable of outputting a series of data bits having timing jitter. Then the data bit stream having timing jitter is input into the receiver. By comparing the input and output test data bit streams, the jitter tolerance of the receiver can be derived.
However, a good jitter generator must be capable of controlling the jitter frequency and the magnitude of the jitter amplitude, where the jitter amplitude represents the amount of the phase shift of the data signal or the clock signal, and the jitter frequency is the times of generating a phase shift. Although on the current market, there are plenty of off-the-rack test instruments that may satisfy this demand, these test instruments, however, are very expensive and not suitable for being tested in mass production. Another prior art solution utilizes a signal generator and a mixer to modulate a clock signal having timing jitter, where the cost of this solution is lower.